1. Field of the Invention
The present invention relates to a semiconductor memory with an error correction function.
2. Description of the Related Art
A semiconductor memory with an error correction function includes regular cell arrays for storing data from the outside, and parity cell arrays for storing parity data of data written into the regular cell arrays. The parity data are generated corresponding to the write data by means of a parity generation circuit. It is therefore not easy to write predetermined data into the parity cell array. In consideration of this problem, there are disclosed technologies in which external parity data terminals for reading data from the parity cell arrays and writing data into the parity cell arrays are formed in a semiconductor memory, and data is directly written into the parity cell arrays and directly read from the parity cell arrays during the test mode, thereby saving test time (for example, Japanese Unexamined Patent Application Publication No. 5-54697).
Meanwhile, the ratio of the parity cell array occupied in the regular cell array is lowered as the bit number of data for generating parity data is increased. Thus, it has small influence on the chip size. For this reason, in this kind of a semiconductor memory, in order to minimize an increase in the chip size, there is a case where parity data are generated using data having a large bit width, which are written into a plurality of regular cell arrays to which different addresses are allocated. In this case, data supplied to external data terminals are written into any one of the regular cell arrays, which is selected according to an address. In parity memory cells, addresses correspond to a plurality of different regular memory cells. Thus, if the external parity data terminals are formed in this kind of the semiconductor memory, an address map of regular cell arrays and an address map of parity cell arrays are different during the test mode where the external parity data terminals are used.
In the event that the aforementioned semiconductor memory is tested, test data supplied to the external data terminals are written into any one of the regular memory cells of the regular cell array according to an address. The test parity data supplied to the external parity data terminals are written into any one of the parity memory cells of the parity cell array according to an address.
As described above, in the test mode, the address maps of the regular cell arrays and the parity cell arrays are different. Due to this, there is no co-relation in physical locations between the regular memory cell into which the test data are written, and the parity memory cell into which the parity test data are written. That is, the regular memory cell and the parity memory cell into which data are written do not exist relatively at the same location within the regular cell arrays and the parity cell arrays. Accordingly, in this kind of the semiconductor memory, there is a problem in that it is difficult to find the relation between a regular cell array where failure has occurred and a parity cell array. Further, in the case where failure occurring due to the interaction between data stored in memory cells is evaluated, it is necessary to generate test patterns for the regular cell array and the parity cell array, respectively, in order to evaluate their interaction. This results in an increase in the number of test patterns to be managed since the design time needed for the test patterns becomes lengthy. Furthermore, in a redundancy decision test for determining the use of a redundancy circuit that corrects failure, a redundancy decision test must be performed on a regular cell array and a parity cell array, respectively. Accordingly, there is a problem in that the test efficiency is low.